Quatech MPA-100 Bedienungsanleitung

MPA-100RS-232 SYNCHRONOUSADAPTER CARDUser's ManualQUATECH, INC. TEL: (330) 665-90005675 Hudson Industrial Parkway FAX: (330) 665-9010Hudson, Ohio

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3. ADDRESSINGThe MPA-100 occupies a continuous 8 byte block of I/O addresses. For example, if thebase address is set to 300H, then the MPA-100 will o

The first four bytes, Base+0 through Base+3, of address space on the MPA-100 containthe internal registers of the SCC. The next two locations Base+4

4. INTERRUPTSThe MPA-100 supports eleven interrupt levels: IRQ2 -7, IRQ10 - 12, and IRQ14 - 15, and selects which interrupt level is in use through

4.1 Using Terminal Count to Generate InterruptsThe MPA-100 allows the option of generating an interrupt whenever the Terminal Count(TC) signal is asse

5. JUMPER CONFIGURATIONSThe MPA-100 utilizes various jumper blocks which allow the user to customize theirhardware configuration. The following secti

5.3 Interrupt Level Selection - J5 & J6 Jumper blocks J5 and J6 select the interrupt level that the MPA-100 utilizes. Interruptlevels IRQ2 - IRQ7

5.4 Transmit DMA Selection - J8 J8 Selects the DMA channel to be used for Transmit DMA. Three channels (1 - 3) areavailable on the MPA-100 for DMA. Wh

NOTE: Since it is illegal to perform DMA on transmit and receive on thesame DMA channel, jumper blocks J7 and J8 should never have thesame pins c

6. SCC GENERAL INFORMATIONThe Serial Communications Controller (SCC) is a dual channel, multi-protocol datacommunications peripheral. The MPA-100 pr

6.1 Accessing the RegistersThe mode of communication desired is established and monitored through the bit valuesof the internal read and write registe

Example 2: Monitoring the status of the transmit and receive buffers in RR0 of Channel A.Register 0 is addressed by default if no register number is

and receive clocks. These clocks can be programmed in WR11 to come from the RTXC pin, theTRXC pin, the output of the BRG, or the transmit output of th

6.2 Baud Rate Generator ProgrammingThe baud rate generator (hereafter referred to as the BRG) of the SCC consists of a 16-bitdown counter, two 8-bit t

6.3 SCC Data Encoding MethodsThe SCC provides four different data encoding methods, selected by bits D6 and D5 inWR10. These four include NRZ, NRZI, F

7. DIRECT MEMORY ACCESSDirect Memory Access (DMA) is a way of transferring data on the ISA bus directly toand from memory, resulting in high data tran

When using the channel A DTR/REQ pin for transmit DMA the SCC must beprogrammed so that the request release timing of this pin is identical to the WAI

8. CONFIGURATION REGISTERThe MPA-100 is equipped with an onboard register used for configuring informationsuch as DMA enables, DMA sources, interrupt

D1 -RXSRC, RECEIVE DMA SOURCE:When set (logic 1), this bit allows the source for Receive DMA to come from theW/REQB pin of channel B on the SCC. W

9. COMMUNICATIONS REGISTERThe MPA-100 is equipped with an onboard Communications Register which gives theuser options pertaining to the clocks and tes

Warranty InformationQuatech Inc. warrants the MPA-100 to be free of defects for one (1) year from the date of purchase. Quatech Inc. wi

D4 -REMOTE LOOPBACK ENABLE:When set (logic 1), this bit allows the DTE to test the transmission path up to and throughthe remote DCE to the DTE int

10. DTE/DCE CONFIGURATIONAs indicated earlier in this manual, the MPA-100 can be configured as either a DataTerminal Equipment (DTE) or a Data Communi

10.1 DTE ConfigurationThe MPA-100 is configured as a DTE device by correctly setting jumper packs J2, J11and J12. See Section 5, Table 3 for this co

The testing signals the DTE can generate are the Local Loopback Test (LL) and theRemote Loopback Test (RL). These signals are generated from the onboa

Control signals the DCE can generate are the Clear to Send (CTS), Carrier Detect (CD),and Data Set Ready (DSR). It can receive the signals Data Termi

Table 17 DCE SignalsINTM or Bit D7 of Comm RegXTMBit D4 of Comm RegXRLBit D5 of Comm. RegXLLRTXC/TRXCB pin of SCCXXRxCLKTRXCA pin of SCCXTxCLKDTR/RE

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11. EXTERNAL CONNECTIONSThe MPA-100 is designed to meet the RS-232 standard through a D-25 connector. TheMPA-100 uses a D-25 short body male connecto

Table 19 DCE Connector Pin DefinitionsD7 of COMM REGXTEST MODE25RTXC pins on SCCXTXCLK (DTE)24---N/C23---N/C22D4 of COMM REGXRL21DCDB on SCCXDTR20---

Figure 6 MPA-100 DTE Output Connector Configuration25 Test Mode (Output)24 TxCLK (DTE)23 N/C22 N/C21 RLBK (Output)20 DTR19 N/C18 LL

The information contained in this document cannot be reproduced in any form without thewritten consent of Quatech, Inc. Likewise, any software progra

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12. DEFINITION OF INTERFACE SIGNALSCIRCUIT AB - Signal Ground CONNECTOR NOTATION: DGND DIRECTION: Not applicableThis conductor directly connects the

CIRCUIT DD -Receiver Signal Element Timing(RxClk - DCE Source) CONNECTOR NOTATION: RXCLK (DCE) DIRECTION: From DCEThis signal, generated by the DCE,

CIRCUIT RL - Remote Loopback  CONNECTOR NOTATION: RLBK DIRECTION: To DCEThis signal provides a means whereby a DTE or a facility test center may che

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13. SPECIFICATIONSBus interface: IBM AT 16-bit bus Controller: Serial Communications Controller, 10 MHz (determined b

MPA-100User's ManualVersion 4.12March 2004Part No. 940-0037-412MPA-100 User's Manual 13-2

Table of Contents13-113. SPECIFICATIONS... .12-112. DEFINITION OF INTERFACE SIGNALS...

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1. INTRODUCTIONThe Quatech MPA-100 is a single channel, synchronous RS-232 compatible serialcommunication port for systems utilizing the architecture

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2. HARDWARE INSTALLATIONIf the default address and interrupt settings are sufficient, the MPA-100 can be quicklyinstalled and put to use. The factory