Quatech MPAP-100 Bedienungsanleitung PDF herunterladen (Seite 47)

Bit 1: RXSRC --- Receive FIFO DMA Source: This

bit determines which SCC pins are used to control transmit and receive DMA

transactions between the SCC and the external FIFOs (when enabled). The

transmit data FIFO is always used with SCC channel A. The receive data FIFO

may be used with SCC channel A by setting RXSRC to logic 0, or with SCC

channel B by setting RXSRC to logic 1. (See page 29 for information on using

channel B.)

W/REQADTR/REQA

Transmit

DMA

W/REQBW/REQAReceive DMA

RXSRC = 1RXSRC = 0

Bit 0: Reserved, always 0.

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Quatech MPAP-100 Bedienungsanleitung Seite 47